Real Time Zetta Bytes -Universal Memory ASIC SOC IP Core Design Implementation using VHDL and Verilog HDL for High Capacity Data Computing Processors like Cloud/Cluster/Super VLIW Parallel Distributing Pipelined Array Computing Processors Journal title: IOSR Journals (IOSR Journal of Computer Engineering) Authors: P.N.V.M Sastry , Dr.D.N.Rao , Dr.S.Vathsal Subject(s):
