32 Bit Parallel Multiplier Using VHDL
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2014, Vol 9, Issue 3
Abstract
In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. Here comparison is done between Carry Save Adder (CSA) and Carry Look Ahead Adder (CLA). The comparison is done on the basis of two performance parameters i.e. Speed and Power consumption. To design an efficient integrated circuit in terms of power and speed, has become a challenging task VLSI design field.
Authors and Affiliations
Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey
Keywords
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