A CONCURRENT ERROR DETECTION SCHEME FOR TOTALLY SELF CHECKING FPGA LOOK-UP TABLE
Journal Title: ICTACT Journal on Microelectronics - Year 2016, Vol 1, Issue 4
Abstract
Field Programmable Gate Arrays are widely useful in mission critical applications. FPGAs have fixed architecture; it has the capability to change function in situ for a particular application. SRAM based FPGAs are vulnerable to Single Event Upsets (SEUs), which poses unintended change to the logic functions on exposure. The project proposed is a unidirectional error detection scheme i.e., Scalable Error Detection Coding (SEDC) scheme, for use in FPGA Look-up tables. The SEDC check bits are generated along with the programming bits and it is stored on the FPGA SRAM cells during the normal operation of the LUTs. The programming bits are processed to check bit generator where corresponding code bits are generated for the programming bits. The newly generated code bits are compared with the pre-stored code bits. Any single or multiple unidirectional errors as a result of SEU is detected by this scheme. Scalability is the significant advantage of this scheme - it can be scaled to any input data length. With the increase in input data length, only the area gets scaled while the latency remains constant irrespective of the binary data length. The implemented algorithm achieves 100% error detection. The Proposed SEDC scheme is simulated using Tanner EDA tool and the layouts are generated using Microwind
Authors and Affiliations
Natarajan S, Deepa V
Keywords
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- EP ID EP198099
- DOI 10.21917/ijme.2016.0026
- Views 169
- Downloads 0
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