A Logic Test to Minimize Test Data Volume By Single Cycle Access Structure
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 9
Abstract
This research proposes a a logic test to min imize test data volume by single cycle access structur e. It eliminates the peak power consumption problem of conventional shiftbased scan chains and reduces th e activity during shift and capture cycles. This leads t o more realistic circuit behavior during stuck at and a tspeed tests. It enables the complete test to run at muc h higher frequencies equal or close to the one in funct ional mode. It will be shown, that a lesser number of t est cycles can be achieved compared to other publish ed solutions. The test cycle per net based on a simple test pattern generator algorithm without test pattern c ompression is below 1 for larger designs and is indep endent of the design size. Results are compared to oth er published solutions on ISCAS’89 net lists. The stru cture allows an additional onchip debugging signal vi sibility for each register. The method is backward co mpatible to full scan designs and existing test pattern generators and simulators can be used with a minor e nhancement. It is shown how to combine the propose d solution with built in self test (BIST) and massive parallel scan chains.
Authors and Affiliations
Chittari Amarnath, K. Bala
Keywords
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