Adaptive Hold Aware Clock Gated MAC
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 9
Abstract
This paper proposed the design of low power Multiply and Accumulate (MAC) Unit utilizing the techniques of Ancient Indian Vedic Mathematics that have been adjusted to enhance performance. The speed of MAC depends incredibly on the multiplier. The work has demonstrated the proficiency of UrdhvaTriyagbhyam– Vedic method for duplication which strikes a distinction in the real procedure of augmentation itself. Low power is the most basic issues in today's ASIC design, as the component size is downsized. Henceforth there is a critical requirement for power improvement. Clock gating is a standout amongst the most exquisite and great techniques for diminishment of dynamic power, significant supporter in all out power utilization of any VLSI circuit. Contrasted with ordinary conventional multiply and accumulate we embraced versatile hold based clock gating for decrease of clock power of gathering of registers utilized of intermitted storage.
Authors and Affiliations
C Ashok Kumar, B. K MADHAVI, K. Lal Kishore
Keywords
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- EP ID EP392376
- DOI 10.9790/9622-0709041317 .
- Views 112
- Downloads 0
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