AISC Implementation of Arithmetic Mean Circuit For High Speed SRAM Applications
Journal Title: International Journal of Engineering and Science Invention - Year 2018, Vol 7, Issue 9
Abstract
In the early part of digital electronic science, the synthesis of circuits are carried out by arithmetic operations has been pivotal. Conventionally, the inspection of arithmetic circuits has been oriented towards general purpose computers, which provide most important applications of digital circuits. Application specific standard product (ASSP) is a more general purpose device that is created by using ASIC tools and technologies. Concurrently, a System on Chip (SOC) is an ASIC or ASSP that acts as entire subsystem. In this paper Arithmetic Mean is designed for High speed SRAM applications. Arithmetic Mean Circuits is designed by using Enhanced Divider Data Path circuit and finally all the blocks are coded using Verilog HDL, simulated (tested) using nchdl simulator and it is synthesized and implemented on Cadence – SOC Encounter using GPDK 45nm Technology Libraries.
Authors and Affiliations
Atchutuni Ashalatha, Thota Rasmitha, Subha Sri Lakshmi. Thiruveedhi
Keywords
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