An Area-Efficient Carry Select Adder Design by using 180 nm Technology
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2013, Vol 4, Issue 1
Abstract
In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.
Authors and Affiliations
Garish Kumar Wadhwa , Amit Grover , Neeti Grover , Gurpreet Singh
Keywords
Related Articles
- EP ID EP135584
- DOI 10.14569/IJACSA.2013.040118
- Views 81
- Downloads 0
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