An Effective Algorithm for Minimizing the Critical Access Time of a 3D-Chip Data Bus
Journal Title: International Journal of Electronics Communication and Computer Engineering - Year 2018, Vol 9, Issue 4
Abstract
A 3D chip exists a natural 3D data bus that integrates all the local data buses located on different stacked layers by vertically connecting a number of TSVs. The critical access time of running data on the 3D data bus dominants the keyed performance of a 3D chip. This paper conducts to minimize the critical access time on a 3D data bus. Based on the topology of a 3D data bus with a number of timing periods for accessing data, an effective algorithm is proposed to insert signal repeaters into the critical access path of the bus and tune their sizes to minimize the critical access time. This procedure is repeated until no additional improvement. For ten tested 3D data buses with various topologies using 45nm technology, experimentally, our algorithm can effectively reduce the critical access time of a 3D data bus up to 86.14% with inserted repeater sizes of 65 on average.
Authors and Affiliations
Chia-Chun Tsai
Keywords
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