An efficient approach to minimize power and area in carry select adder using binary to excess one converter
Journal Title: Acta Technica Napocensis- Electronica-Telecomunicatii (Electronics and Telecommunications) - Year 2013, Vol 54, Issue 2
Abstract
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16, 32, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- nm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. A simple approach is proposed in this paper to reduce the area and power of SQRT CSLA architecture. The compared results show that the modified SQRT CSLA has a slightly larger delay (only 3.76%), but the area and power of the 64-b modified SQRT CSLA are significantly reduced by 17.4% and 15.4% respectively. The power-delay product and also the area-delay product of the proposed design show a decrease for 16, 32, and 64-b sizes which indicates the success of the method and not a mere trade-off of delay for power and area.
Authors and Affiliations
T. CHELLADURA, V. MANIKANDAN, K. RAMAMOORTHY
Keywords
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