An Efficient ASIC Design of RRC FIR Interpolation Filter for wireless Communication Applications
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 1
Abstract
The main objective of pulse shaping filter is to minimize intersymbol interference and shape the signal, In this paper an Application Specific Integrated Circuit (ASIC) is designed using Root Raised Cosine Interpolator Filter by employing multiplier less technique. The transposed direct form II structure of the filter is applied on the cadence platform which ultimately provides the reduced area and high speed. The HDL language is utilized for coding the provided filter specifications, thus the hardware complexity is reduced. The designed filter reduces the area by 40% which improves the hardware architecture. The maximum operating frequency is improved by 18% in comparison to previous work.
Authors and Affiliations
Priyanka Agrawal, Rajesh Mehra
Keywords
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- EP ID EP393422
- DOI 10.9790/9622-0801038185.
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