An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

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An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

Journal Title: Elektronika - Year 2017, Vol 21, Issue 1

Abstract

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and image processing.

Authors and Affiliations

Shoba Mohan, Nakkeeran Rangaswamy

Keywords

Full swing GDI logic array multiplier full adder delay digital circuit hierarchy multiplier carry select adder

EP ID EP360891
DOI 10.7251/ELS1721038M
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