Analysis and Optimization of Level Cache
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 6
Abstract
The focus of this paper is to depict the field of computer architecture, researchers compare architectures by simulating them on a common platform with common benchmark programs. This paper accomplished the following objectives. Designed high level cache architecture with the goal of improving high performance, Low power computing. Compared the new design to existing designs through software simulation. Concluded whether or not the design out-performed existing cache designs in regard to high-performance, low power computing and for determining the new cache configuration. In this paper, we present the different steps of our methodology of adjusting caches for a specific MPSoC application. We have to generate the configuration file where we can find the best configuration with the best size, speed, and associativity for the given application.
Authors and Affiliations
Swati V. Kakde, Mayuri Chawla
Keywords
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