Analysis of 64-Bit Sram Architecture in 90nm Technology Using Dual Threshold Voltage
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 6
Abstract
Static Random Access Memory (SRAM) is a type of memory that is used for high speed and low power applications. As the technology is scaling down, the noise margin of the SRAM cells decreases with the scaling of power supply. The leakage power in the SRAM cells is further increased due to the reduced noise margin. The main objective of this paper is to deal with the power dissipation which occurs normally in the Static Random Access Memory (SRAM) cells during the read and write operation. The 64-bit SRAM architecture is designed using 5T SRAM cell in 90nm technology. The performance of this architecture with its power dissipation and delay are calculated. This is simulated in Cadence Virtuoso Schematic Composer and the Spectre as the simulator.
Authors and Affiliations
K. Vinothini, P. Thiruvalar Selvan
Keywords
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