Analysis of Low Leakage Architecture of SRAM 8x1 Using Leakage Power Reduction Technique in Different Technology
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5
Abstract
as the size of ic’s is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool.
Authors and Affiliations
Sonam Rathore, Sonali Gupta
Keywords
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- EP ID EP24171
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