Area Delay Power Efficient Carry Select Adder for Modern Signal Processors
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
The area, power-efficient and high speed and data path logic systems forms the largest areas of research in VLSI system chip design. The addition speed is limited by the time necessary to send a carry via the adder. Carry Select Adder (CSLA) is the fastest adders used in several data manipulation processors to perform fast arithmetic operation purpose. From the architecture of the CSLA, it is confident for decreasing the area and delay in the CSLA. This project uses a simple and efficient gate level modification is reduces the area and delay of CSLA. Based on this modification 16, 32, 64 and 128-bit square-root Carry Select Adder (SQRT CSLA) architectures have been improved and compared existing SQRT CSLA architecture. The proposed design is less area and delay to a great extent when compared with the regular SQRT CSLA. This project estimates the performance of the designs with the regular designs in terms of delay area and synthesis are implemented in Xilinx FPGA. The results analysis shows that the result is CSLA is better than the regular SQRT CSLA.
Authors and Affiliations
Chandrabose. J, M. Ravikumar
Keywords
Related Articles
- EP ID EP23814
- DOI http://doi.org/10.22214/ijraset.2017.4107
- Views 301
- Downloads 6
Social Engineering
There are several techniques available to a hacker for breaching the Information Security defenses of an organization. The human approach often termed ‘Social Engineering’ and is probably the most difficult one to be de...
Cloud Based E-Rent System
Online reservations give many benefits to users. Rental system also known as hiring, is an agreement where a payment is made for the temporary use of a goods owned by another. It is more convenient and beneficial than p...
Implementation of a Fast Binary Floating Point Dadda Multiplier
This project presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. The design achiev...
Review: Efficient Spam Detection on Social Network
With the rapid growth of social networking sites for communicating, sharing, storing and managing significant information, it is attracting cybercriminals who misuse the Web to exploit vulnerabilities for their illicit...
A Review Paper on PSO and GA Based Optimization for Vehicle Routing Problem
The vehicle routing problem is basically originated from the truck dispatching problem. The VRP is used to design optimal set of routes to serve a given number of customers with a fleet of vehicles. The VRP plays an imp...