Area Delay Power Efficient Carry Select Adder for Modern Signal Processors
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
The area, power-efficient and high speed and data path logic systems forms the largest areas of research in VLSI system chip design. The addition speed is limited by the time necessary to send a carry via the adder. Carry Select Adder (CSLA) is the fastest adders used in several data manipulation processors to perform fast arithmetic operation purpose. From the architecture of the CSLA, it is confident for decreasing the area and delay in the CSLA. This project uses a simple and efficient gate level modification is reduces the area and delay of CSLA. Based on this modification 16, 32, 64 and 128-bit square-root Carry Select Adder (SQRT CSLA) architectures have been improved and compared existing SQRT CSLA architecture. The proposed design is less area and delay to a great extent when compared with the regular SQRT CSLA. This project estimates the performance of the designs with the regular designs in terms of delay area and synthesis are implemented in Xilinx FPGA. The results analysis shows that the result is CSLA is better than the regular SQRT CSLA.
Authors and Affiliations
Chandrabose. J, M. Ravikumar
Keywords
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- EP ID EP23814
- DOI http://doi.org/10.22214/ijraset.2017.4107
- Views 274
- Downloads 6
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