Area Efficient and A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 6
Abstract
Traditional Serial-Serial multiplier addresses the high data sampling rate. It is effectively considered as the entire partial product matrix with n data sampling cycle for n×n multiplication function instead of 2n cycles in the conventional multipliers. This multiplication of partial products by considering two series inputs among which one is starting from LSB the other from MSB. Using this feed sequence and accumulation technique it takes only n cycle to complete the partial products. It achieves high bit sampling rate by replacing conventional full adder and highest 5:3 counters. Here asynchronous 1’s counter is presented. This counter takes critical path is limited to only an AND gate and D flip-flops. Accumulation is integral part of serial multiplier design. 1’s counter is used to count the number of ones at the end of the nth iteration in each counter produces. The implemented multipliers consist of a serial-serial data accumulator module and carry save adder that occupies less silicon area than the full carry save adder. In this paper we implemented model address for the 8bit 2’s complement implementing the Baugh-wooley algorithm and unsigned multiplication implementing the architecture for 8×8 Serial-Serial unsigned multiplication.
Authors and Affiliations
Balakrishna Konda| M.Tech Embedded Systems Sri Vasavi Engineering College Tadepalligudem, West Godavari District. Andhra Pradesh, India, Subbarao Madasu| Assistant Professor, Department of ECE Sri Vasavi Engineering College Tadepalligudem, West Godavari District Andhra Pradesh, India
Keywords
Related Articles
- EP ID EP8328
- DOI -
- Views 405
- Downloads 22
Seamless Mobility in Heterogeneous Mobile Networks
The objective of this paper is to introduce a vertical handover (VHO) algorithm between wireless LANs (WLANs) and LTE mobile networks. The proposed algorithm is based on the fuzzy control theory and takes into conside...
A Novel Approach on DWT Province for Colorant Watermarking
This article aims at lightweight, visionless recognition of additive spread-spectrum watermarks in the DWT domain. We focus on two host signal clatter models and two types of postulate tests for watermark recognition....
MapReduce Based Implementation of Aggregate Functions on Cassandra
MapReduce is a simple and powerful processing model that allows parallel scalable programs to run on large volume of data on massive cluster of computers. Besides, Cassandra is a popular database of NoSQL solutions....
A 0.18?m and 2GHz CMOS Differential Low Noise Amplifier
We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 ?m standard CMOS process. Cadence design tool Spectre_RF is used to design and simula...
A Survey: Feature Extraction Methods for Iris Recognition
The biometrics is the study of physical traits or behavioral characteristics of human include items such as finger prints, face, hand geometry, gait, keystrokes, voice and iris. Among the biometrics, iris has highly accu...