A 0.18?m and 2GHz CMOS Differential Low Noise Amplifier
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 4
Abstract
We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 ?m standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for the design of Differential Low Noise Amplifier. Consuming 9mA current at 1.8V supply voltage, the proposed LNA exhibits a power gain of 15.87 dB, noise Figure (NF) of 2.4 dB, S11 of -9.842 dB and S12 of -42.86dB. The input IP3 (IIP3) at 2 GHz is -2.86127 dBm, and consumes 16.2 mW of power.
Authors and Affiliations
Somesh kumar| Research scholar, Department of Electronics and Communication Thapar University, Patiala, India, Kuldeepak| Research scholar, Department of Electrical and Electronics Y.M.A.C University of Science & Technology Faridabad, India
Keywords
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