Design Of Digital FIR Filter Using LUT Based Multiplier

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Design Of Digital FIR Filter Using LUT Based Multiplier

Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2013, Vol 3, Issue 5

Abstract

In FPGA design the implementation fir filters for DSP applications place an important role. The FPGA area is mainly decided by the number of LUT’s occupied. Hence for any design if the optimisation for the area is carried out for LUT’s, then delay will also reduce. To optimize filters using LUT’s for memory based multiplications, four basic techniques are used from which the combination of two techniques i.e., APC and OMS gave better optimization results. Further if Distributed Arithmetic (DA) technique is utilised for the filter design approach. Then an efficient area implementation can be achieved. In this paper L=2 to 8 bit width based filters are designed and synthesised using Xilinx ISE 10.1i. Nearly 40% area improvement is achieved for approximately same delay.

Authors and Affiliations

Mallela Umamaheswari| M.Tech (VLSI) Student, ECE Department Sri Krishna devaraya Engineering College Gooty, Ananthapur, J Ravi| Associative Professor, ECE Department Sri Krishna devaraya Engineering College Gooty, Ananthapur

Keywords

Field Programmable Gate Array (FPGA) Odd Multiple Storage (OMS) Anti –Symmetric Product Coding (APC) Distributed Arithmetic (DA) and Look Up Table (LUT)

EP ID EP8363
DOI -
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