Area Efficient Low Power Compressor Design Using GDI Technique
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2014, Vol 12, Issue 3
Abstract
Compressors are major components of the present multiplier designs. In multipliers maximum amount of power is consumed during the partial product addition. For higher order multiplication, a huge number of adders or compressors are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor adders are designed by merging binary counter property with compressor property. In this paper, designs of 4:3, 5:3, 6:3, 7:3 compressors based on Gate Diffusion input technique have been presented. The designs are synthesized and analysed using Cadence Virtuoso tool in 180nm technology. When compared with CMOS based compressors, the proposed compressors show reduction in area and power ranging from 38.8% to 65.26% and 33.3% to 40% respectively.
Authors and Affiliations
Nidhi Pokhriyal , Neelam Rup Prakash
Keywords
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