Area Optimized Radix-2 8-Bit Reversible Booth Multiplier
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 10
Abstract
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation and area efficient. Designers „endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of 8 bit Booth‟s multiplier in reversible mode. Booth‟s multiplier is considered as one of the fastest multipliers in literature have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. This paper of 8x8 reversible Radix-2 Booth‟s Multiplier is designed in VHDL and synthesised and simulated in ALTERA QUATRUS –II 9.1. From the results have shown that the proposed design used 140 Combinational ALUTs and operating with 43.64MHz frequency.
Authors and Affiliations
K. Swapna, A. krishna Mohan
Keywords
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- EP ID EP392510
- DOI 10.9790/9622-0710016570.
- Views 72
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