Area reduction in CSLA with efficient delay management
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 2
Abstract
Adders play a key role in the arithmetic processors. There are many ways to design an adder. The major disadvantage of digital adders are that its speed is limited due to delay occurred in carry propagation. Carry select adder (CSLA) is one of the fastest adders used in many computational systems to improve the carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. But the area of CSLA increases with the use of dual RCAs. A CSLA with Binary to Excees-1 Converter (BEC) is designed to reduce the area of the CSLA, but the delay over head is increasing. To further decrease the area and to keep the delay constant or equal as basic CSLA, an add one circuit can be used to design a CSLA. This work proposes the design of 8-bit, 16- bit, 32-bit, 64-bit and 128-bit square root CSLA (SQRT CSLA) using BEC with significant reduction in area.
Authors and Affiliations
Ch Gayatri| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineering & technology, Tagarapulasa, vizianagaram , gayifine148@gmail.com, Mtech (VLSI)| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineering & technology, Tagarapulasa, vizianagaram ,, D Naveen| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineering & technology, Tagarapulasa, vizianagaram ,naveen4u@hotmail.com
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