Characterization of AF Relaying Systems to Analyze the Ceiling Properties in System Limitations
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2014, Vol 4, Issue 6
Abstract
In recen times, it was shown that transceiver hardware impairments have a harmful impact on the performance of communiqué systems, especially for high-rate systems. The vast majority of technical contributions in the area of relaying take for decided perfect transceiver hardware. This paper quantifies the crash of transceiver hardware impairments in dual-hop Amplify-and-Forward relaying, jointly for fixed and variable increase relays. The outage probability in this practical scenario be a function of the instant end-to-end signal-to-noiseand-distortion ratio. This paper derives closed-form expressions for the exact and asymptotic OPs under Rayleigh fading, accounting for hardware impairments at both the transmitter and the communicate One important observation is that for both types of relaying, an increase in the SNRs lead to an “SNDR ceiling” effect, which is explicitly quantified. The value of the SNDR ceiling is inversely proportional to the level of impairments. Physical transceiver hardware introduces impairments that distort the emitted signals. Despite the practical importance of these impairments, little was known about their impact on the achievable performance of relaying systems. This paper has analytically shown that the performance of dual-hop AF relaying is highly affected by these impairments, particularly when high spectral efficiencies are required. In particular, it turns out that for high signal-to-noise ratio, the instantaneous back-to-back SNDR converges to a deterministic constant, called the SNDR ceiling, which is inversely proportional to the level of impairments.
Authors and Affiliations
P. Priyanka| M.Tech Scholar Prasidha college of Engineering and Technology, Anathavaram, India, D. S. Samba Siva Rao| Assistant Professor, Prasidha college of Engineering and Technology, Anathavaram, India
A 0.18?m and 2GHz CMOS Differential Low Noise Amplifier
We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 ?m standard CMOS process. Cadence design tool Spectre_RF is used to design and simula...
Digitally Programmable Four Phase Quadrature Oscillator in Current Mode
A simple technique is presented to realize a digitally programmable current mode four phase quadrature oscillator using MOCCII. The realized oscillator enjoys the attractive features of digital tuning, low component c...
Clustering the Indian States on the Basis of Agriculture Produce of KHARIF and RABI Crops
Agriculture arguably the backbone of India’s economy is highly dependent on spatial and temporal distribution of monsoon rainfalls. This paper represents the concept of clustering and use the centroid based technique k-m...
FPGA Based Implementation of Genetic Algorithm Using VHDL
The research on genetic algorithm is normally concentrate on software Implementation, which is always restricted in term of high real time by computer system because it is serial calculation. This paper introduces a hard...
A Novel A2-based Neural Network Model for Voice Prediction
A novel “Multi-Layer Perceptron” (MLP) model, based on the new A2 arithmetic is investigated in this paper. The already implemented A2 arithmetic operators, such as addition and multiplication are used to predict voi...