Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2014, Vol 10, Issue 11
Abstract
This paper presents a comparative analysis of a 1-bit adiabatic full subtractor designed in 45nm technology node. Adiabatic logic is a low power digital circuit design technique which is much more power efficient than CMOS logic. We designed 1-bit full subtractor using 2N2N2P and DCPAL adiabatic logic styles which are two of the popular adiabatic logic styles. We found that the full subtractor designed using DCPAL saves much more power than 2N2N2P adiabatic logic style, also we simulated our circuits at two different frequencies of 100MHz and 300MHz.
Authors and Affiliations
Nikhil Deo , Rusni Kima Mangang
Keywords
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