Comparison and performance analysis of VLSI adders using 22nm Technology
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 2, Issue 4
Abstract
Speed, power and chip area are the most important goal of the current nano meter technology, so it is very important to design and implement new VLSI circuits. Here we design and compare the various CMOS adders with less number of transistors used. The adders designed are simulated using Ptm22nm technology and simulated by Hspice software. In this paper, we survey various designs of low-power full-adder cells from conventional CMOS. And further describe simulation experiments that compare the simulated full-adder cells. Using the experiments we simulate all combinations of input transitions and measured power and corresponding delay. The simulation results show advantages as well as the disadvantages of the various cell designs.
Authors and Affiliations
Namachivayam S, Rajendiran P, M. E.
Keywords
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