Design and Analysis of Different Circuits using DCVSL & Static CMOS Technique

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Design and Analysis of Different Circuits using DCVSL & Static CMOS Technique

Journal Title: GRD Journal for Engineering - Year 2018, Vol 3, Issue 7

Abstract

The basic requirement of any Integrated Circuit is high speed and low power processing of the data signals to perform the desired execution. The minimization of feature size plays an important role in increasing the performance of integrated circuits. However, the minimization of ICs has affect on leakage current when compared to the total current requirement of the circuit. So in this work presents the design of single bit magnitude comparator & 3 input EXOR gate using conventional CMOS logic style as well as DCVSL style. Then, the comparison has been carried out for both the designs with some parameters. These parameters are power dissipation, delay and how much transistors have been used in the respective designs, and then concluded that which design yields best results accordingly. In CMOS circuits, as the technology scales down to nano scale, the sub-threshold leakage current increases with the decrease in the threshold voltage. So we need a technique to tackle the power dissipation problem in CMOS circuits do the analysis keeping parameters such as power consumption, delay, voltage & transistor count. First, there is the analysis between power consumption & delay, keeping the voltage constant at 5V. We here can see that circuit of the DCSVL structures produces better results in terms of power consumption by lowering its value. The circuit designed using DCVS Logic style is an attempt to further reduce the power dissipation with minimum delay.

Authors and Affiliations

Aradhana Pathak, Mr. Narendra Chaurasiya

Keywords

CMOS DCVSL Magnitude Comparator EXOR Gate VLSI Tanner EDA

EP ID EP375104
DOI -
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