Design and FPGA Implementation of DDR SDRAM Controller
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
Technology is increasing day by day. The world is obsessed with smart phones, laptops and computers. RAM which is used in these devices is the internal memory of CPU for storing data, program and program result. SDRAM or Synchronous Dynamic Random Access Memory is able to work efficiently. It is synchronised with the clock of the processor. The advance version of SDRAM is DDR (Double Data Rate) SDRAM which transfer data on both rising and falling edges of the clock resulting in double data transfer rate. In this paper, DDR SDRAM controller is designed and implemented on FPGA. Transfer rate is 266 M bits/s/pin and clock frequency is 133 MHz This has been done using Verilog HDL on Xilinx ISE 14.2 and finally the controller is targeted to Xilinx Spartan 3E FPGA kit.
Authors and Affiliations
Aadhar Agarwal, Pooja Choudhary, Kalpesh Jain, Chetan Kumhar, Abhiroop Goyal,
Keywords
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- EP ID EP23930
- DOI http://doi.org/10.22214/ijraset.2017.4224
- Views 286
- Downloads 8
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