Design and Implementation of 32-Bit Magnitude Comparator Using Full Adder
Journal Title: IOSR Journals (IOSR Journal of Electrical and Electronics Engineering) - Year 2018, Vol 13, Issue 4
Abstract
In today’s life VLSI plays vital role for low power consumption, small area and fast response of the electronic devices. Here 32-bit magnitude comparator is designed taken into account of low power, small area and less delay. For this novel magnitude comparator designing full adder is used .Full adder gives two outputs sum and carry which is equivalent to the output of comparator ‘s equal and smaller respectively.
Authors and Affiliations
Raman Shrivastav, Shweta Agrawal
Keywords
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- EP ID EP388903
- DOI 10.9790/1676-1304020104.
- Views 137
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