Design and Implementation of 4-bit Pipeline ADC using 0.09µm CMOS Technology

Abstract

This paper focuses on design and implementation of 1.1V, 4-bit Pipeline Analog to Digital Converter [ADC]. The ADC consists of sample and hold, latched comparator and summing circuit and amplifier of gain 2. The ADC has been designed and simulated in standard gpdk90ηm CMOS technology library using Cadence tool.

Authors and Affiliations

Mr. Vishwanath Lakkannavar

Keywords

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  • EP ID EP220453
  • DOI -
  • Views 126
  • Downloads 0

How To Cite

Mr. Vishwanath Lakkannavar (2014). Design and Implementation of 4-bit Pipeline ADC using 0.09µm CMOS Technology. International journal of Emerging Trends in Science and Technology, 1(3), 388-392. https://europub.co.uk/articles/-A-220453