Design and implementation of 4-bit Vedic Multiplier
Journal Title: International journal of Emerging Trends in Science and Technology - Year 2016, Vol 3, Issue 5
Abstract
Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance .The need of high speed multiplier is increasing as the need of high speed processors are increasing . A Multiplier is one of the key hardware blocks in most fast processing system which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction
Authors and Affiliations
Anannya Maiti
Keywords
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