Design and realization of DPLL based on VHDL

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Design and realization of DPLL based on VHDL

Journal Title: Science Paper Online - Year 2007, Vol 2, Issue 6

Abstract

The principle of the Digital Phase Locked Loop has been discussed in order to improve the synchronization of the digital communication system and to make the system stable and reliable. A kind of DPLL bit synchronization implementation method has been designed , all based on digital circuits. And the system is designed using VHDL. In allusion to the character of signal prone to be interfered, an integral circuit is designed instead of a differential circuit. At the same time an adaptive module joins for the purpose of adjusting the controversy of PLL speed of phase adjustment and the ability of disturbance rejection. With the better ability of disturbance rejection, DPLL can adjust the phase rapidly to achieve the locked state. The VHDL program was simulated in maxplus2.The simulation results are presented and prove the validity of the design.

Authors and Affiliations

Dong Yan

Keywords

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EP ID EP91432
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