Design and Verification of ACK / NAK Protocol of PCI Express Data Link Layer in System Verilog.
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 12
Abstract
PCI-Express is a high performance, general purpose I/O interconnect communication protocol for multiplexing various peripheral. PCI Express is third generation Computer Bus(3GIO) to inter connect peripherals in a Computer, Servers, Mobile sets and systems. It is the layered, packet approach serial bus protocol. And the transfer rate of GEN 4 PCI-Express is up to 16GTps, and the throughput is around 2GBps for X1 lane. It has three major layers -Transaction Layer, Data Link Layer and Physical Layer. The basic objective of this project is to designing and verifying the ACK/ NAK Protocol of PCI-Express Data Link Layer. The Primary responsibility of this layer is to assure the integrity of TLPs moving between devices, but it is also plays a part in TLP flow control, Link initialization and power management and convey information between the Transaction Layer above it and the Physical Layer below it. In performing this job, the Data Link Layer exchanges packets with its neighbor know as Data Link Layer Packets (DLLPs). DLLP are communicating between the Data Link Layers of each device. DLLPs of Data Link layer supports ACK / NAK Protocol. This work uses System Verilog to model different blocks of the ACK / NAK Protocol of Data Link Layer layer of PCI Express. The RTL code is designed and Verified using the ModelSim-Altera 6.3g_p1 (Quartus II 8.1) Web Edition.
Authors and Affiliations
Gokulakrishnan S, Radhakrishnan N
Keywords
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