Design of a 12-Bit 200MS/S CMOS Sample-and-Hold Circuit
Journal Title: روش های هوشمند در صنعت برق - Year 2014, Vol 5, Issue 18
Abstract
In this paper, a new 12bit, 200MS/s fully differential sample and hold circuit is presented. In order to increase the linearity and input voltage dynamic range; bootstrapped-switches are used for sampling the input signal. Furthermore, a tunable gain buffer is used as the output stage of the circuit to prevent the loading effects of the succeeding stages on the proposed circuit. The circuit is simulated in HSPICE using 0.35µm CMOS technology parameters. As it is discussed in the paper, simulation results justify the good performance of the proposed circuit for using in 12bit, 200MS/s applications.
Authors and Affiliations
Hamid Mahmoodian, Mehdi Dolatshahi
Keywords
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- EP ID EP328646
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