Design of A High Speed And Low Power 4 Bit Carry Skip Adder
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 3
Abstract
This paper focuses on carry skip adder (CSKA) structure that has a higher speed yet lower power consumption compared with the conventional one. The speed enhancement is achieved by applying Transmission gate logic (TG) to improve the efficiency of the conventional CSKA structure. The CMOS multiplexer in Conventional CSKA is replaced by multiplexer using transmission gate for the skip logic in proposed CSKA. The structure may be realized with transmission gate multiplexer that improves the speed and delay parameters of the adder. The simulation of this CSKA is done using TANNER EDA. Finally, a low power and high speed proposed structure is implemented, which lowers the power consumption without considerably impacting the speed. The proposed structures are assessed by comparing their speed, power, and delay parameters with those of other existing adders using a 45-nm CMOS technology for a wide range of supply voltages.
Authors and Affiliations
Khushbu Nagori, Suman Nehra
Keywords
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- EP ID EP390850
- DOI 10.9790/9622- 0703056669.
- Views 168
- Downloads 0
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