VLSI Modeling of High Performance Aging Aware Multiplier By Using Adaptive Hold Logic Circuit
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 2
Abstract
Digital multipliers are most critical Arithmetic Logic Units. The performance of ALU systems depends on the throughput of the multiplier. In VLSI, the negative bias temperature instability effect occurs when a pmos Transistor is under negative bias. This result in increasing the threshold voltage of pmos transistor. This phenomenon seriously reduces the speed of multiplier. Similarly th positive bias instability occurs when an nmos transistor is under positive bias. These positive and negative biasing effects degrade the speed of multiplier,degrade the speed of transistor and in long term, the system may fail due to timing violations. In this paper we proposed to design a reliable high performance multiplier with a novel Adaptive Hold Logic(AHL) circuit. With AHL the multiplier is able to provide a higher throughput. The design is implemented by using Advanced design tools like Xilinx14.3 ISE Design suite. The experimental results shows that the proposed architecture yields high performance when compare to the Exixting Architecture.
Authors and Affiliations
P. Lokesh, U. Somalatha, S. Chandana
Keywords
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- EP ID EP393730
- DOI 10.9790/9622-0802030712.
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