Design of Asynchronous Viterbi Decoder using VHDL for Low Power Consumption
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 4
Abstract
In today’s digital communication systems, Convolutional codes are widely utilize in channel coding techniques. The Viterbi decoder due to its efficient performance is broadly used for decoding the convolution codes. Developments in the communication field have created a demand for high speed and low power Viterbi decoders with long battery life, low power dissipation and low weight. This paper describes the design of an asynchronous l∕3 rate frequency 5MHz and constraint length K=3 Viterhi decoder using VHDL and power analysis on FPGA.
Authors and Affiliations
Gaurav S. Wairagade , Surekha K. Tadse
Keywords
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