Design of Built-in Self-Repair Strategy with Selectable Redundancy for Embedded SRAM
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 9
Abstract
The main strategy of this project is to design a fault diagnoses system for detection and repair of any permanent failures or faults in the embedded read only memories. Built-In Self-Repair (BISR) with redundancy is an effective scheme for embedded memories. Each fault address can be saved only once is the feature of the proposed BISR strategy and is flexible with four operating modes. In BIAA module, fault addresses and redundant ones form a one-to-one mapping to achieve a high repair speed. March algorithms for testing memories and their fault coverage are compared. Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. Instead of adding spare words, spare rows, spare columns or blocks in the SRAMs, normal words can be used as redundancy.
Authors and Affiliations
Gandla Nataraju, Aleti Shanker
Keywords
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