Design of Co-Processor for NIOS-II Processor Based Poly phase Image Scalar
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 3
Abstract
In this paper, we present an hardware accelerating coprocessor for a Polyphase image scaler. First the image scaling algorithm will be ported onto the SOC having Altera NIOSII processor which will be a pure software implementation then a poly-phase FIR filter will be designed in hardware. This hardware FIR filter will be interfaced to NIOS II processor as coprocessor. After interfacing with this coprocessor the performance of poly-phase image scaler is improved and this will demonstrate the software hardware codesign. The total solution will be generic and can be used in the video surveillance applications too.
Authors and Affiliations
Venkata Sateesh Raja, T. Sreenivasu, Addanki Purna Ramesh
Keywords
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