Design of Dadda Algorithm based Floating Point Multiplier
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 11
Abstract
In this paper area efficient floating point multiplier is developed using Dadda Algorithm . For improving the speed of mantissa multiplication Dadda multiplier is used by replacing Carry Save Multiplier. The use of proposed Multiplier Algorithm reduces the area than the previous one and the significant delay is also lower than the previous de-signs. The number of slices in the previous designs is 648 and in our proposed Dadda Multiplier architecture utilizes only 402 slices then area is reduced up to 30%. As shown in the design as well as the simulation results the proposed multiplier architecture area as well as delay is better.
Authors and Affiliations
A. Bhanu Swetha, V. Ramoji, S. Raghava Rao
Keywords
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- EP ID EP28351
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