Self-Checking Carry-Select Adder Design Based on Two-Pair Two-Rail Checker

Abstract

In the design of integrated circuits error checking And area occupancy plays a vital role because of increasing the necessity of portable systems. InThis paper, the self-checking carry-select adder (CSeA) design is proposed. The capability of self checking can detect transient and all single stuck-at faults on-line in normal operation mode. The proposed CSeA has not only having self-checking capability but also have reduced transistor count. The reduced ratio of transistorcount is proportional to the bit count of self-checking CSeA to be designed. Our design has other advantages such as high extensibility, non-tree detector structure, and reasonable propagation delay time and can keeping well normal operation in the high-bit design.This paper focuses on self-checking carry-select adder design based on two-pair two-rail checker(TTRC). The resulting carry-select adders have capability to detect errors on-line during the normal operation, with reduced silicon area with lower power consumption.

Authors and Affiliations

P. S. D. Lakshmi, K. Srinivas, R. Satish Kumar

Keywords

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  • EP ID EP28362
  • DOI -
  • Views 317
  • Downloads 4

How To Cite

P. S. D. Lakshmi, K. Srinivas, R. Satish Kumar (2015). Self-Checking Carry-Select Adder Design Based on Two-Pair Two-Rail Checker. International Journal of Research in Computer and Communication Technology, 4(12), -. https://europub.co.uk/articles/-A-28362