Design of Energy Efficient and Size Reduced Scram Cell
Journal Title: IOSR journal of VLSI and Signal Processing - Year 2018, Vol 8, Issue 3
Abstract
Semiconductor memories are a vital component of essentially any state of the art digital circuits. One among them is the Static Random Access Memory (SRAM). The dynamic power consumption contributes to about 80% of the total power consumption. In this paper a novel 4T asymmetric SRAM Cell is proposed which has reduced the dynamic power consumption by 98.58% and area occupied by 30.86% when compared to one of the existing 4T SRAM Cells. This cell is designed using 45nm technology.
Authors and Affiliations
Sanjay G1 ,, Shruthi J1 ,, Suraj N. K1 ,, Roopa K Swamy1
Keywords
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