Design of High Speed Low Power Multiplier Using Nikhilam Sutra with Help of Reversible Logic
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 1
Abstract
Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as " Nikhilam Sutra multiplier”. The ―Nikhilam Navatascaram Dasatah literally means ―All from Nine and the last from Ten. The sutra basically means start from the left most digit and begin subtracting ‗9‘ from each of the digits; but subtract ‗10‘ from the last digit.This will be implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.
Authors and Affiliations
Manjeet Sankhwar
Keywords
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