Design of Improved Array Multiplier by Carry Select Logic
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 4
Abstract
Multiplier is such an important element from the point of power consumption and speed of operation in the system. Multiplication using deletion scheme provides an efficient method for reducing the power and area as compared to that of full width multiplier. This paper is about the implementation of array multiplier using carry select adder for improving speed of operation of the multiplier. Array multipliers with deletion scheme offer significant improvement in area, delay & power. The proposed method finally reduces a set of full adders by carry select adder. While implementing this proposed method experimentally, delay in operation can be saved.
Authors and Affiliations
Silpa Raj P, Punitha V
Keywords
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- EP ID EP20239
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