DESIGN OF LOW POWER 32-BIT CSKA FOR HIGH SPEED APPLICATIONS
Journal Title: Elysium Journal of Engineering Research and Management - Year 2015, Vol 6, Issue 5
Abstract
Research in Very Large Scale Integration (VLSI) based design of Integrated Circuits (IC) addresses the issues of power, area and time consumption by the components used. These violates the speed of operation in DSP processors. To improve the speed, an optimized Design is required in such a way that the utilization of components are less. The inclusion of Multiplier and Accumulator (MAC) unit in the DSP processor Design performs the number of operation by using adders. Hence, the reduction in power, area and time in full adder is the necessary process in low power applications. Modern DSP processors uses the carry chain for optimization in carry forwarding path which reduces the delay effectively. The Carry Select Adder (CSLA) is the prominent solution to improve the speed of parallel operation. But, the result contains more number of carriers. Hence, multiplexers are used for selection of required sum output and associated carry. This paper optimizes the carry forwarding path by replacing the multiplexers with the Boolean function based gate construction. Moreover, the employment of carry-skip mechanism reduces the number of components required to design a 32-bit ripple carry adder. Besides, the application of Microwind- DSCH tool to create the layout of corresponding 32 bit adder. The DSCH tool visualizes the carry forwarding path and the time required to perform the operation effectively. The optimization provided in adder structure enhances the operational speed with minimum area occupation and power consumption.
Authors and Affiliations
Yamini C. , Krishnamurthy M
Keywords
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