Design of Low Power FPGA using Autonomous Power Gating and LEDR Encoding
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 10
Abstract
The most important key challenge in the IC scaling era is to deliver high performance solutions in the process of minimizing power, area and cost. The main objective of this paper is to reduce power consumption by considering power optimization techniques using Low Power FPGA design. Due to the dynamic properties of power consumptions this paper focuses on some of the power gating techniques that is standby power and dynamic power can be reduced by LEDR (LEVEL ENCODING DUAL RAIL) Encoding. The proposed autonomous fine grain power gating method consists of LUTs. Each LUT has its own sleep transistor & sleep controller. So when any one of LUTs are inactive, they can be set to sleep mode immediately. Another proposed method is LEDR encoding is used to data flow at I/P and O/P of FPGAs. Hence power reduction is achieved by selectively setting the functional units into a low leakage mode when they are inactive.
Authors and Affiliations
Sandhya Rani. P, Venkata Satish. N
Keywords
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