Design of Parallel MAC Based On Radix-4 & Radix-8 Modified Booth Algorithm
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 7
Abstract
This paper focused on a combined process of multiplication and accumulation based on radix-4 & radix-8 booth encodings. In this Paper, we investigate the method of implementing the Parallel MAC with the smallest possible delay. Parallel MAC is frequently used in digital signal processing and video/graphics applications. A new architecture of multiplier - and accumulator (MAC) for highspeed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The MAC provides high speed multiplication and multiplication with accumulative addition. Enhancing the speed of operation of the parallel MAC is a major design issue. modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library.
Authors and Affiliations
S. Anitha, M. Vidya, D. Mahesh Varma
Keywords
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