Design Techniques For Low Power Implicit Pulse Triggered Circuits
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 12
Abstract
In Integrated circuits, the portion of the on chip power is covered by clock distribution network, flip-flops and latches. Flip flops and latches absorb large amount of power due to redundant transitions and clocking system. In this paper low power flip-flops are presented. The single edge triggered conditional data mapping flip-flop(CDMFF) and clocked pair shared flipflop(CPSFF) are explained and compared with proposed flip-flop. The proposed flip-flop uses the double edge triggering technique by reducing the frequency to half. These flip-flops are simulated in HSPICE of 0.18μm CMOS technology with a power supply of 1.8V and a frequency of 50MHZ.
Authors and Affiliations
Smt. A. Rajani, A. Yamini
Keywords
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- EP ID EP21455
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