Differentiate Different Methodology for Design of Vedic Multiplier

Abstract

Multiplier is one of the most important part in any processor speed which improves the speed of the operation for example in special application processors like Digital Signal Processor (DSPs). Basically, the operational speed of any digital signal processor is strictly dependent upon the speed of the multipliers used. This paper presents the comparative study of design methodology of Urdhva Tiryakbhyam multiplier on various performance factors like power, delay, space, speed. This paper gives information of “Urdhva Tiryakbhyam” algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed, power and area of multipliers. Proposed design is simulated using ISim and synthesized using Xilinx ISE 14.5. When compared with Mux based Vedic multipliers, proposed design shows a significant improvement in speed.

Authors and Affiliations

Neha Tyagi, Neeraj Kumar Sharma

Keywords

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  • EP ID EP24581
  • DOI -
  • Views 329
  • Downloads 7

How To Cite

Neha Tyagi, Neeraj Kumar Sharma (2017). Differentiate Different Methodology for Design of Vedic Multiplier. International Journal for Research in Applied Science and Engineering Technology (IJRASET), 5(6), -. https://europub.co.uk/articles/-A-24581