DIMINISHING IMPACTS OF VARIOUS OPTIMIZATION TECHNIQUES IN STRONG INVERSION AND SUBTHRESHOLD REGION AT 22NM TECHNOLOGY NODE WITH CMOS BULK MODEL
Journal Title: Indian Journal of Scientific Research - Year 2017, Vol 8, Issue 1
Abstract
The objective of the research work is to show that at advanced technology nodes like 22nm CMOS technology, the various optimization techniques have little or no impact on propagation delay, power or PDP. This is more so in the subthreshold region of 22nm technology node.HSPICE simulator has been used to simulate the NAND CMOS circuits, with and without FG technique and analyze them. Floating gate technique on CMOS NAND gate shows the reduction in power along with reduction in PDP in strong inversion region. Operation of the same circuit in subthreshold region shows the decreased power, increased delay but reduced PDP comparatively. The impact of floating gate technique is less comparatively, in subthreshold region at 22nm technology node. As expected, forward body biasing results in reduced delay and high power but the impact is less at an advanced technology node of 22nm as compared to 350nm/180nm technology. There is only 1.3% reduction in power of NAND CMOS circuit in subthreshold region with forward body bias. In subthreshold region with forward body bias, the floating gate technique has almost no impact on power and propagation delay. This experimental finding opens the future scope of the research to analyze the reasons behind the reducing impacts of optimization techniques at advanced technology nodes of 22nm or so.
Authors and Affiliations
SHOBHA SHARMA
Keywords
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