DSP Based Vedic Multiplier
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 8
Abstract
Digital signal processors (DSPs) are very imperative in various methodological field in the at hand scenario. In today’s world Fast burgeoning is one of the very important methods in DSPs. Fast multiplication is used for intricacy, Fourier Analysis etc. A fastest technique for multiplication based on ancient Indian Vedic arithmetic is proposed in this paper. Among the poles apart methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam will be discussed in detail. Urdhva tiryakbhyam is one of the widespread multiplication formulae pertinent to different cases of multiplication. This is a highly modular drawing in which smaller blocks can be used to build higher blocks. The proposed architecture is done for two 8-bit numbers; the multiplier and multiplicand, each are grouped as 4-bit statistics so that it decomposes into 4×4 multiplication modules. It is also illustrated that the further hierarchical decomposition of 4×4 modules into 2×2 modules will not have a significant effect in improvement of the multiplier efficiency or in other words multiplier decomposition nearly reaches a saturation level in its efficiency at 4×4 decomposition. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series [1]. The combinational delay obtained after synthesis is compared with the performance of the modified Booth Wallace multiplier which is a fast multiplier. This Vedic multiplier can bring about great improvement in DSP performance.
Authors and Affiliations
Abdul Lateef Haroon P. S, Mamatha. G. M
Keywords
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