Dynamic power model of clock networks with transmission line effects
Journal Title: Science Paper Online - Year 2008, Vol 3, Issue 1
Abstract
The size of the present VLSI (very large scale integrated) circuits scales down to deep sub micrometer, and the interconnector exhibits transmission line effects at high clock speed. However, the conventional power models did not consider these effects. Considering transmission line effects, a novel dynamic power model of clock networks is proposed. The input admittance function of clock networks, where transmission line model in all of branches, is computed iteratively based on Fourier series analysis. Based on this iterative method, dynamic power consumption of clock networks is approximated by the summation of the first Fourier-series based terms according to Parseval’s theorem. The accuracy of the model improves with the number of terms and the computational complexity of the model is linearly proportional to the number of terms and the number of branches in clock networks. Experimental results show that the model error is less than 5% and the efficiency is significantly higher than SPICE (simulation program with integrated circuit emphasis).
Authors and Affiliations
LI Xiaochun YIN Wenyan
Keywords
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